In addition to supporting 56G interfaces, DSFP also supports future 112G interfaces. In the field of switching ASICs, with the rise of 56G PAM4 and 112G PAM4 Serdes, the use of PAM4 on the server NIC side and TOR switch side will be the mainstream. 100G QSFP28 is likely to become history, and the next-generation 100G and 200G QSFP56 may become the application direction of servers and TOR switches in the future. As one of the PAM4 application interfaces supporting 50G and 100G, DSFP is compatible with 100G and 200G, and will definitely have a place in future data center applications. Compared with QSFP56 and subsequent QSFP112G, DSFP occupies a smaller volume and can connect more servers.
At the current stage, the Serdes of 112G PAM4, whether it is a switching chip or an optical module, is still in the design stage. After the subsequent technology matures and large-scale commercial use, 2×112G DSFP will also be widely used. In addition, just as QSFP-DD doubles the density of QSFP56, DSFP MSA also proposes an upgraded version of DSFP, DSFP-DD. DSFP-DD is double-density and also uses 50G PAM4 Serdes, but the Serdes channel is doubled to 4 channels, so it can support 4×50G=200G rate transmission, and in the future it can support 4×100G=400G rate .
DSFP-DD is backward compatible with DSFP, adding 21 pins while keeping the 22 pins of DSFP unchanged, and the total number of pins is 43 pins. Similar to QSFP-DD, the Cage size and SMT connector size of DSFP-DD become wider and deeper to accommodate more pins. However, the current state of DSFP-DD is immature, and there is no more detailed specification, and it is expected that there will be updates in the future.
In order to communicate and promote the application of DSFP interface in data centers, this paper introduces the main characteristics of DSFP interface, and introduces its hardware design, power level and interface monitoring experience in detail. Through the example of TOR switch with 48×DSFP+8×QSFP-DD, various configuration application scenarios of its ports are introduced. At the end of the article, the future development of DSFP in the data center is also prospected. The introduction of this paper has a certain reference value for the further application research of DSFP in the future.
On the basis of referring to the DSFP MSA specification, combined with the actual use of the switch, this paper provides a method including hardware interface circuit design, power level and interface monitoring. Compared with MSA, hardware circuit design saves devices and simplifies design. In addition, the monitoring method of the interface has been verified to be reliable and effective. At present, the 1U TOR switch designed in this paper is being used in an Internet client room after full testing. Complying with the current white-box trend of switches, the DSFP-related design methods and applications introduced in this article can provide valuable references for other users, and are also of great help to the promotion of DSFP interface applications.
However, due to the big difference in pin definitions, the DSFP interface is not friendly in terms of downward interface (SFP28) and hardware interface compatibility. At the same time, reducing the speed of DSFP from 100G to 25G causes a great waste of resources, which is why it is not recommended to be compatible with DSFP and SFP28 on the same hardware.
However, on the other hand, for ordinary 25G NRZ switching ASICs, two 25G lanes can be combined on one port by using the DSFP interface, which saves the panel space of the switch and can connect more server ports.
